1. Field of the Invention
The present invention relates to a bus circuit, in particular, to a bus circuit which includes a plurality of signal lines.
2. Description of the Background Art
A semiconductor integrated circuit device is formed of a plurality of circuit blocks represented by an operation unit or a memory. Data exchange among circuit blocks within the semiconductor integrated circuit device is, in general, carried out by using a signal line.
FIG. 11 is a block diagram of a conventional bus circuit within a semiconductor integrated circuit device.
Referring to FIG. 11, a plurality of circuit blocks 3, respectively, have input/output circuits 2. Respective input/output circuits 2 are connected to a signal line 1. Input/output circuits 2 include drivers 6 and receivers 7. Drivers 6 output data from circuit blocks 3 to signal line 1. Receivers 7 receive data from signal line 1. Here, though three circuit blocks are shown in FIG. 1, a plurality of additional circuit blocks may be included.
In order to prevent a plurality of circuit blocks 3 from transmitting data at the same time, circuit blocks 3 cannot transmit data unless the usage right for signal line 1 is acquired. Arbitration of the usage right of the signal line 1 among the circuit blocks is carried out by a dedicated control circuit (not shown).
In FIG. 11, circuit blocks 3 which have, respectively, one input/output circuit 2 are connected to one signal line 1. 1 bit of data is transmitted on one signal line. Conventionally, a data processing unit of a circuit block 3 is not 1 bit but is 32 bits, or more. Accordingly, in practice there are 32, or more, signal lines 1 within the bus circuit and a circuit block 3 has a plurality of input/output circuits 2 connected to respective signal lines.
In recent years the process dimensions of a semiconductor integrated circuit device have become scaled and, as a result, the amount of data which can be processed by a circuit block 3 within the bus circuit at one time has increased from 32 bits to 64 bits or, further, to 128 bits, or more.
FIG. 12 is a circuit diagram of a driver 6 in FIG. 11.
Referring to FIG. 12, driver circuit 6 includes inverters 62, 63, a NAND gate 61 and a NOR gate 64. Inverter 62 includes a P channel MOS transistor 621 and an N channel MOS transistor 622. A driver signal EN is a signal which is inputted to NAND gate 61 and is inputted to NOR gate 64 via inverter 63 and is a signal which is inputted from the outside in order to activate driver 6.
In a circuit block 3 which has acquired the bus usage right, driver activation signal EN is set to an active condition (H level). Therefore, driver 6 outputs a signal of H level from driver 62 when data signal D is at H level and outputs a signal of L level when data signal D is at L level. In addition, in a circuit block 3 which has not acquired the bus usage right, driver activation signal EN is set at L level. Therefore, P channel MOS transistor 621 and N channel MOS transistor 622 in driver 6 are both turned off and, as a result, driver 6 is converted to a high impedance condition.
On the other hand, a receiver 7 receives the entirety of the data on signal line 1. The received data is transmitted to circuit block 3 and the circuit block determines whether or not the received data is utilized. Through the above operation, data exchange is carried out among circuit blocks 3 within the bus circuit.
FIG. 13 is a circuit diagram showing 3 signal lines for transmitting data signals among a plurality of signal lines within the bus circuit.
Referring to FIG. 13, a signal line BUS2 is a signal line neighboring signal lines BUS1 and BUS3. Signal line BUS2 transfers a data signal D, signal lines BUS1 transfers a data signal Dnxe2x88x921 and signal lines BUS3 transfers a data signal Dn+1, respectively. In addition, drivers DR1 to DR3 are, respectively, connected to one end of signal lines BUS1 to BUS3. Furthermore, receivers RV1 to RV3 are, respectively, connected to the other end of signal lines BUS1 to BUS3.
Here, the wire capacitance which is driven when driver DR2 outputs data signal Dn to signal line BUS2 is described.
First, the case where data signals Dn+1 and Dnxe2x88x921 change while in a phase opposite to that of data signal Dn is described.
At this time, capacitance Cm between wires for data signal Dn and data signal Dn+1 appears twice as large as it actually is due to the Miller effect because when the potential of capacitance Cm between wires at one terminal C1 changes from power source potential VDD to ground potential GND, the potential of capacitance Cm between wires at the other terminal C2 changes from ground potential GND to power source potential VDD. Therefore, the amount of relative potential change from terminal C1 to terminal C2 becomes 2VDD.
In the same manner, capacitance Cm between wires for data signal Dn and Dnxe2x88x921 appears twice as large as it actually is.
From the above, a wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (1).
Cn=2Cm+2Cm+CL=4Cm+CLxe2x80x83xe2x80x83(1) 
wherein CL is a capacitance between the signal line and the ground.
Next, the case where data signals Dn+1 and Dnxe2x88x921 change while in the same phase as that of data signal Dn is described.
At this time, potential difference between terminals of capacitance Cm between wires does not occur. Accordingly, wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (2).
Cn=CLxe2x80x83xe2x80x83(2) 
Next, the case where data signals Dn+1 and Dnxe2x88x921 do not change and only data signal Dn changes is described.
At this time, the Miller effect does not occur with capacitance Cm between wires. Accordingly, wire capacitance Cn that must be driven in order for driver DR2 to output data signal Dn onto signal line BUS2 is given in the following equation (3).
Cn=Cm+Cm+CL=2Cm+CLxe2x80x83xe2x80x83(3) 
In the conventional bus circuit, since capacitance CL between the signal line and the ground is larger than capacitance Cm between wires, the transmission speed of a data signal is not affected by a change of a data signal on the neighboring signal line. However, in recent years, miniature processing technology for signal lines has progressed and, therefore, signal line pitches have become narrower. As a result, capacitance Cm between wires has become larger than capacitance CL between the signal line and the ground.
Here, a change of transmission speed of a data signal in the case that a data signal on a neighboring signal line has changed relative to data signal Dn on signal line BUS2 in FIG. 13 is described.
The amount of time for data signal Dn to change from power source potential VDD or ground potential GND to VDD/2 is defined as a data signal transmission time xcex94t. Data signal transmission time xcex94t is approximated in the next equation (4).
xcex94t=VDDxc3x97Cn/ID/2xe2x80x83xe2x80x83(4) 
wherein ID is an average current driving force of the driver.
For example, it is assumed that capacitance Cm between wires/ground capacitance CL is 2. In the case that data signals Dn+1 and Dnxe2x88x921 change while in a phase opposite to that of data signal Dn, a data signal transmission time xcex94t1 of data signal Dn is given in the following equation from equations (1) and (4).
xcex94t1=VDDxc3x97(4Cm+CL)/2ID=9VDDxc3x97CL/2IDxe2x80x83xe2x80x83(5) 
In addition, in the case that data signals Dn+1 and Dnxe2x88x921 change while in the same phase as that of data signal Dn, a data signal transmission time xcex94t2 of data signal Dn is given in the following equation from equations (2) and (4).
xcex94t2=VDDxc3x97(CL)/2ID=VDDxc3x97CL/2IDxe2x80x83xe2x80x83(6) 
From the above results, the maximum value of a data signal transmission time xcex94t of data signal Dn may be nine times larger than the minimum value thereof due to a change of the data signal on a signal line neighboring signal line BUS2.
The operational speed of a semiconductor integrated circuit device is determined by the slowest operation case.
As a result of the above, though scaled physical dimension of signal lines reduces the capacitance between the signal line and the ground, it increases the capacitance between wires and slows the operational speed.
A measure for solving this problem has been proposed in Japanese Patent Laying-Open No. 8-102491(1996).
FIG. 14 is a circuit diagram showing three signal lines for transmitting data signals among a plurality of signal lines within a bus circuit.
Referring to FIG. 14, in this bus circuit 100, a repeater RP0 is inserted only into signal line BUS2 of signal lines BUS1 to BUS3 of which the signal line length is L. Repeater RP0 is inserted into a place halfway from the start of the signal line length L. The other parts of the circuit configuration are the same as in FIG. 13. Repeater RP0 inverts and outputs inputted data signal Dn.
In bus circuit 100, segments where data signals of neighboring signal lines BUS1 to BUS3 are in opposite phases occupy half of the signal line length. Accordingly, a slowing of operational speed of the bus circuit can be prevented.
As described above, in the bus circuit proposed in Japanese Patent Laying-Open No. 8-102491(1996), at least one repeater is inserted into only an odd numbered series of signal lines or into only an even numbered series of signal lines from among a plurality of signal lines. The inserted repeater reduces segments where data signals in opposite phases run at the same time in neighboring signal lines. Therefore, the bus circuit can prevent a slowing of the operational speed.
However, since in the bus circuit proposed in Japanese Patent Laying-Open No. 8-102491(1996) a repeater is inserted into only an odd numbered series of signal lines or into only an even numbered series of signal lines from among a plurality of signal lines, only data signals in the signal lines into which repeaters are inserted are slowed. Accordingly, the timing of signal change shifts between a data signal of a signal line into which a repeater is inserted and a data signal of a signal line into which a repeater is not inserted.
By inserting amplifiers, of which the number is equal to the number of inserted repeaters, into a signal line into which no repeaters RP0 are inserted, the shift of the timing of the signal change can be eliminated. For example, by inserting one amplifier to, respectively, signal lines BUS1 and BUS3, the shift of the timing of the signal change of the data signal inputted from receiver RV1 to 3 is eliminated. However, the insertion of the amplifiers increases the power consumption of the bus circuit.
A purpose of this invention is to provide a bus circuit that can prevent a slowing of operational cycle time without a shift of the time of the signal change among the signal lines.
A bus circuit according to this invention includes a plurality of signal lines for transmittig data and repeaters for logically inverting data which are provided for respective signal lines wherein at least one repeater is provided for each signal line so that segments for transmitting data in the opposite phase is restricted to half of the signal line length in neighboring signal lines.
Thereby, capacitance between wires of signal lines is lowered. As a result, the operational speed of the bus circuit is prevented from being slowed.
Preferably, a plurality of signal lines include first segments wherein repeaters are provided only for an odd numbered series of signal lines and second segments, of which the segment length is equal to that of the first segments and wherein repeaters are provided only for an even numbered series of signal lines, and the first segments and the second segments are arranged in an alternating manner in accordance with the signal line length.
Thereby, the circuit design of a bus circuit becomes easy in accordance with the signal line length.
Preferably, the signal line transfers data in one direction.
Preferably, the signal line transfers data in two directions.
Preferably, the signal line is connected to a plurality of circuit blocks.
Preferably, the plurality of circuit blocks are operation units.
Preferably, the plurality of circuit blocks are memories.
A bus circuit design method according to this invention is a bus circuit design method for designing a bus circuit which includes a plurality of signal lines for transmitting data and includes the step of preparing first segments wherein repeaters for logically inverting data are provided only for an odd numbered series of signal lines and second segments, of which the segment length is equal to that of the first segments and wherein repeaters are provided only for an even numbered series of signal lines, the step of determining the numbers of the first segments and the second segments to be arranged in response to the set length of the signal line and the step of alternately placing the first segments and the second segments in accordance with the determined numbers of segments.
As described above according to the present invention, the operational speed of a bus circuit is not slowed by inserting repeaters into the signal lines so that the segments wherein data signals in the opposite phases that run together between neighboring signal lines become half of the signal line length. In addition, the slowing of the operational speed can be prevented by activating only the repeaters which correspond to the direction of the data signal flow even in bi-directional signal lines.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.